Among known non-volatile semiconductor memory devices, there is such a one shown in FIG. 8 (related art 1; see Patent document 1). The non-volatile semiconductor memory device, pertaining to the related art 1, includes, in its memory cell array, a plural number of first diffusion regions 107, a plural number of select gates 103, a plural number of floating gates 106 and a plural number of control gates 111.
The first diffusion regions 107 extend in one direction on the surface of a substrate 101 and are separated one from another. The first diffusion regions 107 are used as local bitlines (LB). The select gates (SG) 103 are arranged in regions on the substrate sandwiched between neighboring ones of the first diffusion regions 107, with the interposition of a plural number of insulating films 102, and are extended along the extending directions of the first diffusion regions 107. The floating gates (FG) 106 are storage nodes and are arranged in regions defined between the first diffusion regions 107 and the select gates 103, with the interposition of the insulating films 102. When seen in a plan view, the floating gates look like islands. The control gates (CG) 111 are arranged on the top of the floating gates 106 and the select gates 103, with the interposition of a plural number of insulating films 108. The control gates 111 are arranged in juxtaposition, with an interval from one another, and are extended in a direction of crossing the select gates 103. The control gates 111 are used as wordlines.
One 107 out of the first diffusion regions 107, lying on either sides of the select gate 103, the floating gate 106, the control gate 111 and the select gate 103 make up a first unit cell. The other 107 of the first diffusion regions 107, lying on either sides of the select gate 103, the floating gate 106, the control gate 111 and the select gate 103, make up a second unit cell. The first diffusion region 107 is shared by a plural number of unit cells. With this non-volatile semiconductor memory device, an inversion layer 120 is formed on the surface of the substrate 101 below the select gate 103 in the cell region.
The voltages applied to the first diffusion region 107, select gate 103, control gate 111 and to the substrate 101 (well 101a) is controlled by a driving circuit, not shown, constituting a portion of a peripheral circuit in the semiconductor memory device.
The erasure operation by the non-volatile semiconductor memory device, according to the related art 1, is described as follows.
Referring to FIG. 8, in the first erasure operation, a high negative voltage is applied to the control gate 111, whilst a high positive voltage is applied to the substrate 101 (well 101a). For example, a voltage Vcg=−9V is applied to the control gate 111, and a voltage Vsub=9V is applied to the substrate 101 (well 101a). The first diffusion region 107 and the select gate 103 are open. In this state, electrons e are extracted from the floating gate 106 to the substrate 101 (well 101a) as shown by the arrows e. The potential Vfg of the floating gate 106 at the time of the first erasure operation can be calculated by the following equation 1:
                              Vfg          =                                    Q              Call                        +                                          Ccf                Call                            ⁢              Vcg                        +                                          Cfsub                Call                            ⁢              Vsub                                      ⁢                                  ⁢                  Call          =                      Ccf            +            Csf            +            Cfsub                          ⁢                                  ⁢                              Vcg            <                          0              ⁢              V                                ,                      Vsg            =                          open              ≡                              0                ⁢                                                                  ⁢                V                                              ,                      Vsub            >                          0              ⁢              V                                                          [                  Equation          ⁢                                          ⁢          1                ]            where Q denotes the quantity of electricity of the floating gate 106, Ccf denotes the capacitance between the control gate 111 and the floating gate 106, Cfsub denotes the capacitance between the floating gate 106 and the substrate 101, and Csf denotes the capacitance between the select gate 103 and the floating gate 106.
Referring to FIG. 9, in the second erasure operation, a negative high voltage is applied to the control gate 111, and a positive voltage is applied to the select gate 103. For example, a voltage Vcg=−9V is applied to the control gate 111, and a voltage Vsg=3V is applied to the select gate 103, whilst the first diffusion region 107 and the substrate 101 (well 101a) are open. In this state, electrons e are extracted from the floating gate 106 to the select gate 103 as shown by arrows e. The potential Vfg of the floating gate 106 at the time of the second erasure operation can be calculated by the following equation 2:
                              Vfg          =                                    Q              Call                        +                                          Ccf                Call                            ⁢              Vcg                        +                                          Csf                Call                            ⁢              Vsg                                      ⁢                                  ⁢                  Call          =                      Ccf            +            Csf            +            Cfsub                          ⁢                                  ⁢                              Vcg            <                          0              ⁢              V                                ,                      Vsg            >                          0              ⁢              V                                ,                      Vsub            =                          open              ≡                              0                ⁢                V                                                                        [                  Equation          ⁢                                          ⁢          2                ]            where Q denotes the quantity of electricity of the floating gate 106, Ccf denotes the capacitance between the control gate 111 and the floating gate 106, Cfsub denotes the capacitance between the floating gate 106 and the substrate 101, and Csf denotes the capacitance between the select gate 103 and the floating gate 106.
[Patent document 1] JP Patent Kokai Publication No. JP-P2005-51227A
The disclosure of the Patent document 1 is herein incorporated by reference thereto.